|
English
|
正體中文
|
简体中文
|
2815447
|
|
???header.visitor??? :
27402906
???header.onlineuser??? :
777
???header.sponsordeclaration???
|
|
|
|
???tair.name??? >
???browser.page.title.author???
|
"lee jri"???jsp.browse.items-by-author.description???
Showing items 1-10 of 23 (3 Page(s) Totally)
1 2 3 > >>
View [10|25|50] records per page
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet
|
Wu, Ke-Chung;Lee, Jri; Wu, Ke-Chung; Lee, Jri; JRI LEE |
| 國立臺灣大學 |
2005-06 |
A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-/spl mu/m CMOS technology
|
Lee, Jri; Ding, Jian-Yu; Cheng, Tuan-Yi |
| 國立臺灣大學 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri |
| 臺大學術典藏 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri; Lee, Jri |
| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
| 國立臺灣大學 |
2008 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, Mingchung |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, M. |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
|
Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
A 20Gb/s Duobinary Transceiver in 90nm CMOS.
|
Lee, Jri;Chen, Ming-Shuan;Wang, Huaide; Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE |
| 國立臺灣大學 |
2006 |
A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology
|
Lee, Jri |
Showing items 1-10 of 23 (3 Page(s) Totally)
1 2 3 > >>
View [10|25|50] records per page
|
